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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___pll_param.html">XHdmiphy1_PllParam</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for CPLL/QPLL programming.  <a href="struct_x_hdmiphy1___pll_param.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html">XHdmiphy1_Channel</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for PLL type and its reference clock.  <a href="struct_x_hdmiphy1___channel.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___mmcm.html">XHdmiphy1_Mmcm</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for MMCM programming.  <a href="struct_x_hdmiphy1___mmcm.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___quad.html">XHdmiphy1_Quad</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef represents a GT quad.  <a href="struct_x_hdmiphy1___quad.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___log.html">XHdmiphy1_Log</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains the logging mechanism for debug.  <a href="struct_x_hdmiphy1___log.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___hdmi21_cfg.html">XHdmiphy1_Hdmi21Cfg</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains the HDMI 2.1 FRL configurations.  <a href="struct_x_hdmiphy1___hdmi21_cfg.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___config.html">XHdmiphy1_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for the Video PHY core.  <a href="struct_x_hdmiphy1___config.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_hdmiphy1.html" title="The XHdmiphy1 driver instance data. ">XHdmiphy1</a> driver instance data.  <a href="struct_x_hdmiphy1.html#details">More...</a><br/></td></tr>
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Typedefs</h2></td></tr>
<tr class="memitem:ga5ff00002844b75068ea21b03514fcf04"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga5ff00002844b75068ea21b03514fcf04">XHdmiphy1_IntrHandler</a> )(void *InstancePtr)</td></tr>
<tr class="memdesc:ga5ff00002844b75068ea21b03514fcf04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Callback type which represents the handler for interrupts.  <a href="group__xhdmiphy1.html#ga5ff00002844b75068ea21b03514fcf04">More...</a><br/></td></tr>
<tr class="separator:ga5ff00002844b75068ea21b03514fcf04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7c61707222943633f7df3de4acf2d51a"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga7c61707222943633f7df3de4acf2d51a">XHdmiphy1_TimerHandler</a> )(void *InstancePtr, u32 MicroSeconds)</td></tr>
<tr class="memdesc:ga7c61707222943633f7df3de4acf2d51a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Callback type which represents a custom timer wait handler.  <a href="group__xhdmiphy1.html#ga7c61707222943633f7df3de4acf2d51a">More...</a><br/></td></tr>
<tr class="separator:ga7c61707222943633f7df3de4acf2d51a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga14ce1c0f480526922f42b9e7ff8dee8f"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga14ce1c0f480526922f42b9e7ff8dee8f">XHdmiphy1_Callback</a> )(void *CallbackRef)</td></tr>
<tr class="memdesc:ga14ce1c0f480526922f42b9e7ff8dee8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Generic callback type.  <a href="group__xhdmiphy1.html#ga14ce1c0f480526922f42b9e7ff8dee8f">More...</a><br/></td></tr>
<tr class="separator:ga14ce1c0f480526922f42b9e7ff8dee8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga503c2ff79c8d1c28506c02d3be634763"><td class="memItemLeft" align="right" valign="top">typedef u64(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga503c2ff79c8d1c28506c02d3be634763">XHdmiphy1_LogCallback</a> )(void *CallbackRef)</td></tr>
<tr class="memdesc:ga503c2ff79c8d1c28506c02d3be634763"><td class="mdescLeft">&#160;</td><td class="mdescRight">Generic callback type.  <a href="group__xhdmiphy1.html#ga503c2ff79c8d1c28506c02d3be634763">More...</a><br/></td></tr>
<tr class="separator:ga503c2ff79c8d1c28506c02d3be634763"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadcff193d2a45fbd03c48f595fe8fdf55"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gadcff193d2a45fbd03c48f595fe8fdf55">XHdmiphy1_ErrorCallback</a> )(void *CallbackRef)</td></tr>
<tr class="memdesc:gadcff193d2a45fbd03c48f595fe8fdf55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error callback type.  <a href="group__xhdmiphy1.html#gadcff193d2a45fbd03c48f595fe8fdf55">More...</a><br/></td></tr>
<tr class="separator:gadcff193d2a45fbd03c48f595fe8fdf55"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Enumerations</h2></td></tr>
<tr class="memitem:ga3f9002a6b4bc8e47f9c1fa68f8d0fb15"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga3f9002a6b4bc8e47f9c1fa68f8d0fb15">XHdmiphy1_ProtocolType</a> </td></tr>
<tr class="memdesc:ga3f9002a6b4bc8e47f9c1fa68f8d0fb15"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef enumerates the various protocols handled by the Video PHY controller (HDMIPHY).  <a href="group__xhdmiphy1.html#ga3f9002a6b4bc8e47f9c1fa68f8d0fb15">More...</a><br/></td></tr>
<tr class="separator:ga3f9002a6b4bc8e47f9c1fa68f8d0fb15"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0babc37b8b55084caeefe57eef4fbd62"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga0babc37b8b55084caeefe57eef4fbd62">XHdmiphy1_IntrHandlerType</a> </td></tr>
<tr class="memdesc:ga0babc37b8b55084caeefe57eef4fbd62"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef enumerates the list of available interrupt handler types.  <a href="group__xhdmiphy1.html#ga0babc37b8b55084caeefe57eef4fbd62">More...</a><br/></td></tr>
<tr class="separator:ga0babc37b8b55084caeefe57eef4fbd62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8df8a80a15683dd3ffe31d80780f6329"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga8df8a80a15683dd3ffe31d80780f6329">XHdmiphy1_HdmiHandlerType</a> { <a class="el" href="group__xhdmiphy1.html#gga8df8a80a15683dd3ffe31d80780f6329a96b12cc5ff9908c81fcb6231b7aec8ac">XHDMIPHY1_HDMI_HANDLER_TXINIT</a> = 1, 
<a class="el" href="group__xhdmiphy1.html#gga8df8a80a15683dd3ffe31d80780f6329ae806cfadcc91063cd2bbeb8482f79433">XHDMIPHY1_HDMI_HANDLER_TXREADY</a>, 
<a class="el" href="group__xhdmiphy1.html#gga8df8a80a15683dd3ffe31d80780f6329a57c314d217e86af61f9e4e7d6e446e83">XHDMIPHY1_HDMI_HANDLER_RXINIT</a>, 
<a class="el" href="group__xhdmiphy1.html#gga8df8a80a15683dd3ffe31d80780f6329a419d981d4a35b761784f48e87adba9b3">XHDMIPHY1_HDMI_HANDLER_RXREADY</a>
 }</td></tr>
<tr class="memdesc:ga8df8a80a15683dd3ffe31d80780f6329"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef enumerates the list of available hdmi handler types.  <a href="group__xhdmiphy1.html#ga8df8a80a15683dd3ffe31d80780f6329">More...</a><br/></td></tr>
<tr class="separator:ga8df8a80a15683dd3ffe31d80780f6329"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8559ee2ca7c404467a72f4653a5d4f5"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gae8559ee2ca7c404467a72f4653a5d4f5">XHdmiphy1_PllType</a> </td></tr>
<tr class="memdesc:gae8559ee2ca7c404467a72f4653a5d4f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef enumerates the different PLL types for a given GT channel.  <a href="group__xhdmiphy1.html#gae8559ee2ca7c404467a72f4653a5d4f5">More...</a><br/></td></tr>
<tr class="separator:gae8559ee2ca7c404467a72f4653a5d4f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga54f72201d2012e3c638ec92b5e310f23"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> </td></tr>
<tr class="memdesc:ga54f72201d2012e3c638ec92b5e310f23"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef enumerates the available channels.  <a href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">More...</a><br/></td></tr>
<tr class="separator:ga54f72201d2012e3c638ec92b5e310f23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaec55cf3dfcfa0c7cf9749c63690dd019"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> </td></tr>
<tr class="memdesc:gaec55cf3dfcfa0c7cf9749c63690dd019"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef enumerates the available reference clocks for the PLL clock selection multiplexer.  <a href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">More...</a><br/></td></tr>
<tr class="separator:gaec55cf3dfcfa0c7cf9749c63690dd019"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d998790546ec3dde5119376868686e6"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a> </td></tr>
<tr class="memdesc:ga4d998790546ec3dde5119376868686e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef enumerates the available reference clocks used to drive the RX/TX datapaths.  <a href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">More...</a><br/></td></tr>
<tr class="separator:ga4d998790546ec3dde5119376868686e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac87909fabb3f765c0be156e7082aea8e"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gac87909fabb3f765c0be156e7082aea8e">XHdmiphy1_SysClkOutSelType</a> </td></tr>
<tr class="memdesc:gac87909fabb3f765c0be156e7082aea8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef enumerates the available reference clocks used to drive the RX/TX output clocks.  <a href="group__xhdmiphy1.html#gac87909fabb3f765c0be156e7082aea8e">More...</a><br/></td></tr>
<tr class="separator:gac87909fabb3f765c0be156e7082aea8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b751875671500e5b0173be954368177"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga1b751875671500e5b0173be954368177">XHdmiphy1_OutClkSelType</a> </td></tr>
<tr class="memdesc:ga1b751875671500e5b0173be954368177"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef enumerates the available clocks that are used as multiplexer input selections for the RX/TX output clock.  <a href="group__xhdmiphy1.html#ga1b751875671500e5b0173be954368177">More...</a><br/></td></tr>
<tr class="separator:ga1b751875671500e5b0173be954368177"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga19e4c793abee3457123797eca4f61cd0"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga19e4c793abee3457123797eca4f61cd0">XHdmiphy1_GtState</a> { <br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga19e4c793abee3457123797eca4f61cd0abb6da8fd6d31dd97dea1910021b0d8f7">XHDMIPHY1_GT_STATE_IDLE</a>, 
<a class="el" href="group__xhdmiphy1.html#gga19e4c793abee3457123797eca4f61cd0a8237da6c8720d2611ec2eb56927e9fd6">XHDMIPHY1_GT_STATE_GPO_RE</a>, 
<a class="el" href="group__xhdmiphy1.html#gga19e4c793abee3457123797eca4f61cd0aeb66246b5c2c3de1c42d34fc8a5a9de2">XHDMIPHY1_GT_STATE_LOCK</a>, 
<a class="el" href="group__xhdmiphy1.html#gga19e4c793abee3457123797eca4f61cd0adbd966511bbee7acb1ce508578605fb6">XHDMIPHY1_GT_STATE_RESET</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga19e4c793abee3457123797eca4f61cd0a540efa0ad171c67927e0364e77bf0ab0">XHDMIPHY1_GT_STATE_ALIGN</a>, 
<a class="el" href="group__xhdmiphy1.html#gga19e4c793abee3457123797eca4f61cd0af0bd0b978b52982e2caf6a30afc3f57d">XHDMIPHY1_GT_STATE_READY</a>
<br/>
 }</td></tr>
<tr class="separator:ga19e4c793abee3457123797eca4f61cd0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga507763f75897762cabf8819fde24ab8f"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga507763f75897762cabf8819fde24ab8f">XHdmiphy1_LogEvent</a> { <br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa05c6742ec935bcbad19af54685b3d9f5">XHDMIPHY1_LOG_EVT_NONE</a> = 1, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa91285a2fe900849e83aa45be23b8fc31">XHDMIPHY1_LOG_EVT_QPLL_EN</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa2f2949d1be35d7c96902fe8b031d6251">XHDMIPHY1_LOG_EVT_QPLL_RST</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fae542d14fe31f4366262597571621900b">XHDMIPHY1_LOG_EVT_QPLL_LOCK</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fad1a525f5335b7c7814e19fc19e8dee78">XHDMIPHY1_LOG_EVT_QPLL_RECONFIG</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8faab11ea8cc0444e9eaebfc01d2e25c2e1">XHDMIPHY1_LOG_EVT_QPLL0_EN</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa544654893a30ea4372fde78d3da63efe">XHDMIPHY1_LOG_EVT_QPLL0_RST</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fab7973c8195409260d4b4c17edd2107f6">XHDMIPHY1_LOG_EVT_QPLL0_LOCK</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa9730d0f429cc284bf9239c464962514f">XHDMIPHY1_LOG_EVT_QPLL0_RECONFIG</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fad12d4e763346f6f277aaaeee968f9b1b">XHDMIPHY1_LOG_EVT_QPLL1_EN</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa8f6ebe550852ace5dcb397e0e92e7de5">XHDMIPHY1_LOG_EVT_QPLL1_RST</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa99870e5fedc372c2161de8f595976c89">XHDMIPHY1_LOG_EVT_QPLL1_LOCK</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa4d242a87ab686b95bf2ce14ca72001e8">XHDMIPHY1_LOG_EVT_QPLL1_RECONFIG</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa7a74c2aff0510429874c8467fbfa720b">XHDMIPHY1_LOG_EVT_PLL0_EN</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fabb0430d0b85286e505c0f956279edd68">XHDMIPHY1_LOG_EVT_PLL0_RST</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fab13829acbd775009fcc1f01514a9fe91">XHDMIPHY1_LOG_EVT_PLL1_EN</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fad9ca01949d854ce10d3bc43a5ca215a8">XHDMIPHY1_LOG_EVT_PLL1_RST</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa6291555f8d5842b49cc85b1992b93171">XHDMIPHY1_LOG_EVT_CPLL_EN</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa84d8493337faf9af93ce135edca252ae">XHDMIPHY1_LOG_EVT_CPLL_RST</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fadb7701b9317cdb208995d002892d0eac">XHDMIPHY1_LOG_EVT_CPLL_LOCK</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fafe46d81b98d1f454e167f1850d51e73c">XHDMIPHY1_LOG_EVT_CPLL_RECONFIG</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa8579679c6be1018462759ab6d24f694a">XHDMIPHY1_LOG_EVT_LCPLL_LOCK</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa88ab82faf45e848827696960f46af78b">XHDMIPHY1_LOG_EVT_RPLL_LOCK</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fab85fcce757da0b66c9944fa7f7d75eef">XHDMIPHY1_LOG_EVT_TXPLL_EN</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8faed656efbf8d1665cc583db964226960a">XHDMIPHY1_LOG_EVT_TXPLL_RST</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fab005d48a1421a996107763e25a79ed6a">XHDMIPHY1_LOG_EVT_RXPLL_EN</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa34f1adc5b5220146133d12c5c673c466">XHDMIPHY1_LOG_EVT_RXPLL_RST</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fab48a003daba5c49c31327d31a7344fdb">XHDMIPHY1_LOG_EVT_GTRX_RST</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fae3b7e5bdbde62c0539b69660ff718a2f">XHDMIPHY1_LOG_EVT_GTTX_RST</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa6ba098981c6f7e8717ab0b3d166facdc">XHDMIPHY1_LOG_EVT_VID_TX_RST</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa3dbbacab895e2f48455597b95f20d3e6">XHDMIPHY1_LOG_EVT_VID_RX_RST</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa4977e4ce8c8d2017bbc96f3675325b99">XHDMIPHY1_LOG_EVT_TX_ALIGN</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8faac936f6bc91762d6621757e29b471994">XHDMIPHY1_LOG_EVT_TX_ALIGN_TMOUT</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fafed065faee2d08d40b502fff4c292445">XHDMIPHY1_LOG_EVT_TX_TMR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8faf2277760e6b71229d82ecf73f95201da">XHDMIPHY1_LOG_EVT_RX_TMR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fab037d8fe4e7d9efa115f91602c0e19d5">XHDMIPHY1_LOG_EVT_GT_RECONFIG</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fac9bbc691736d2c3f8ecf4456e98b7b18">XHDMIPHY1_LOG_EVT_GT_TX_RECONFIG</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa1950033e842d74ae93cf70842b6f9f03">XHDMIPHY1_LOG_EVT_GT_RX_RECONFIG</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8faec83e85f882616806c051d6280541031">XHDMIPHY1_LOG_EVT_INIT</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8facd89910057776a6a302595c1e6aaf263">XHDMIPHY1_LOG_EVT_TXPLL_RECONFIG</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8faf0cd31f3544b0433a61a07313f7306c4">XHDMIPHY1_LOG_EVT_RXPLL_RECONFIG</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa56be305ac94b4fde45ed7f96f2f60416">XHDMIPHY1_LOG_EVT_RXPLL_LOCK</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8faecedb4454e45d609203050d25fb628a9">XHDMIPHY1_LOG_EVT_TXPLL_LOCK</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8faf1558ff041531923de26d2cdf21faeb5">XHDMIPHY1_LOG_EVT_TX_RST_DONE</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa07750319efaea19cbec4aa97eab21bee">XHDMIPHY1_LOG_EVT_RX_RST_DONE</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa8e08806e0035981f0aeac11963e9b29d">XHDMIPHY1_LOG_EVT_TX_FREQ</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa7e97df6b0482956381f42935d4088413">XHDMIPHY1_LOG_EVT_RX_FREQ</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa9bd193450a0b8149982ea2bd8e4b334b">XHDMIPHY1_LOG_EVT_DRU_EN</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fad1249231d3dd37dc9b246750de6c468a">XHDMIPHY1_LOG_EVT_TXGPO_RE</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fab5aab4974e5d695941267b02c063b6bf">XHDMIPHY1_LOG_EVT_RXGPO_RE</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fae974e310d8245fa9285d8a3d460c6701">XHDMIPHY1_LOG_EVT_FRL_RECONFIG</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa924af29f57a82f33882dce6c2de2215b">XHDMIPHY1_LOG_EVT_TMDS_RECONFIG</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa737d1a41d1b1a576101bd574080f08d1">XHDMIPHY1_LOG_EVT_1PPC_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa618c0fbfd33c119da0e2b28cf514972d">XHDMIPHY1_LOG_EVT_PPC_MSMTCH_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fab28d0791b29cf76ead1a21aef864e70c">XHDMIPHY1_LOG_EVT_VDCLK_HIGH_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fad34e90440aa943deb81d65f994e7272b">XHDMIPHY1_LOG_EVT_NO_DRU</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fac16c7e8601244f595cd804fe75df142b">XHDMIPHY1_LOG_EVT_GT_QPLL_CFG_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa1591a806934dc21fa2368d022cd0f12d">XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa4f69c113ecd57c23854146858f0c9269">XHDMIPHY1_LOG_EVT_GT_LCPLL_CFG_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa31b63c120656778e61b40ac16e914019">XHDMIPHY1_LOG_EVT_GT_RPLL_CFG_ERR</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa1c67cc48ccc5a88ac43e15fe694879b6">XHDMIPHY1_LOG_EVT_VD_NOT_SPRTD_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fae623db986f9d02253c3ccbec9f5c6963">XHDMIPHY1_LOG_EVT_MMCM_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa53ab59ff98e6c0f14d01b573c1adb9ad">XHDMIPHY1_LOG_EVT_HDMI20_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fab955fbee9a933ef6bbebf9d04a8ad1db">XHDMIPHY1_LOG_EVT_NO_QPLL_ERR</a>, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa16d87e8ac61927ee62d631af02a55eea">XHDMIPHY1_LOG_EVT_DRU_CLK_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fabf63790d5f5a16fdfbbd3c5d2680fa29">XHDMIPHY1_LOG_EVT_USRCLK_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fa087c065913419984d661cf0488fe3e7e">XHDMIPHY1_LOG_EVT_SPDGRDE_ERR</a>, 
<a class="el" href="group__xhdmiphy1.html#gga507763f75897762cabf8819fde24ab8fac5e344d7d6b6232fbba3fa5698de8532">XHDMIPHY1_LOG_EVT_DUMMY</a>
<br/>
 }</td></tr>
<tr class="separator:ga507763f75897762cabf8819fde24ab8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga99fd3078ca6a97efc41ebae0ab9848b4"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga99fd3078ca6a97efc41ebae0ab9848b4">XHdmiphy1_HdmiTx_Patgen</a> { <br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga99fd3078ca6a97efc41ebae0ab9848b4a2287e71d5eb5822fdad68ffc7014727d">XHDMIPHY1_Patgen_Ratio_10</a> = 0x1, 
<a class="el" href="group__xhdmiphy1.html#gga99fd3078ca6a97efc41ebae0ab9848b4a4cd912ee1ca0dcf2908d7da89aa67a8b">XHDMIPHY1_Patgen_Ratio_20</a> = 0x2, 
<a class="el" href="group__xhdmiphy1.html#gga99fd3078ca6a97efc41ebae0ab9848b4a2110a4eeb03152e3beed98547b3ae92c">XHDMIPHY1_Patgen_Ratio_30</a> = 0x3, 
<a class="el" href="group__xhdmiphy1.html#gga99fd3078ca6a97efc41ebae0ab9848b4a35d0720f27d6bb3698e239fe2a9e79dd">XHDMIPHY1_Patgen_Ratio_40</a> = 0x4, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga99fd3078ca6a97efc41ebae0ab9848b4a54e14196cdba218c9339ab646bc6f183">XHDMIPHY1_Patgen_Ratio_50</a> = 0x5
<br/>
 }</td></tr>
<tr class="separator:ga99fd3078ca6a97efc41ebae0ab9848b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3532b332baefc7e9454c8d485aedb4c9"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga3532b332baefc7e9454c8d485aedb4c9">XHdmiphy1_PrbsPattern</a> { <br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga3532b332baefc7e9454c8d485aedb4c9ae0898365a0b18b77ba8aa9ff62ae6cc8">XHDMIPHY1_PRBSSEL_STD_MODE</a> = 0x0, 
<a class="el" href="group__xhdmiphy1.html#gga3532b332baefc7e9454c8d485aedb4c9af6f4f716f17df5edd1159f6ef190beaa">XHDMIPHY1_PRBSSEL_PRBS7</a> = 0x1, 
<a class="el" href="group__xhdmiphy1.html#gga3532b332baefc7e9454c8d485aedb4c9a2b2bcf27a138709fe68eeb64196d905b">XHDMIPHY1_PRBSSEL_PRBS9</a> = 0x2, 
<a class="el" href="group__xhdmiphy1.html#gga3532b332baefc7e9454c8d485aedb4c9a902b603e09315a9fd882d54c5931ead9">XHDMIPHY1_PRBSSEL_PRBS15</a> = 0x3, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga3532b332baefc7e9454c8d485aedb4c9a160dcf174e121f49389ebffbcaad1b9d">XHDMIPHY1_PRBSSEL_PRBS23</a> = 0x4, 
<a class="el" href="group__xhdmiphy1.html#gga3532b332baefc7e9454c8d485aedb4c9a6e33841bd8f7289de780ffc2448f34a5">XHDMIPHY1_PRBSSEL_PRBS31</a> = 0x5, 
<a class="el" href="group__xhdmiphy1.html#gga3532b332baefc7e9454c8d485aedb4c9af77b0f4ab5babf65a0564dee707db0a3">XHDMIPHY1_PRBSSEL_PCIE</a> = 0x8, 
<a class="el" href="group__xhdmiphy1.html#gga3532b332baefc7e9454c8d485aedb4c9ad3ac6e5e70273461a0d7dd7b8f354d63">XHDMIPHY1_PRBSSEL_SQUARE_2UI</a> = 0x9, 
<br/>
&#160;&#160;<a class="el" href="group__xhdmiphy1.html#gga3532b332baefc7e9454c8d485aedb4c9ad41202a47ce4ece76aab4ec3fe631a7a">XHDMIPHY1_PRBSSEL_SQUARE_16UI</a> = 0xA
<br/>
 }</td></tr>
<tr class="memdesc:ga3532b332baefc7e9454c8d485aedb4c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef enumerates the available PRBS patterns available from the.  <a href="group__xhdmiphy1.html#ga3532b332baefc7e9454c8d485aedb4c9">More...</a><br/></td></tr>
<tr class="separator:ga3532b332baefc7e9454c8d485aedb4c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gac17db2af38544c85cb299d147fcdac16"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">XHdmiphy1_CfgInitialize</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="struct_x_hdmiphy1___config.html">XHdmiphy1_Config</a> *ConfigPtr, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:gac17db2af38544c85cb299d147fcdac16"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function retrieves the configuration for this Video PHY instance and fills in the InstancePtr-&gt;Config structure.  <a href="group__xhdmiphy1.html#gac17db2af38544c85cb299d147fcdac16">More...</a><br/></td></tr>
<tr class="separator:gac17db2af38544c85cb299d147fcdac16"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga82f13f4133bdf9ab03d845c8462dc091"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga82f13f4133bdf9ab03d845c8462dc091">XHdmiphy1_PllInitialize</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, <a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> QpllRefClkSel, <a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> CpllxRefClkSel, <a class="el" href="group__xhdmiphy1.html#gae8559ee2ca7c404467a72f4653a5d4f5">XHdmiphy1_PllType</a> TxPllSelect, <a class="el" href="group__xhdmiphy1.html#gae8559ee2ca7c404467a72f4653a5d4f5">XHdmiphy1_PllType</a> RxPllSelect)</td></tr>
<tr class="memdesc:ga82f13f4133bdf9ab03d845c8462dc091"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will initialize the PLL selection for a given channel.  <a href="group__xhdmiphy1.html#ga82f13f4133bdf9ab03d845c8462dc091">More...</a><br/></td></tr>
<tr class="separator:ga82f13f4133bdf9ab03d845c8462dc091"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6a4e05c5b6141f00bdfa2ae1f30b15a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaf6a4e05c5b6141f00bdfa2ae1f30b15a">XHdmiphy1_GetVersion</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaf6a4e05c5b6141f00bdfa2ae1f30b15a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will obtian the IP version.  <a href="group__xhdmiphy1.html#gaf6a4e05c5b6141f00bdfa2ae1f30b15a">More...</a><br/></td></tr>
<tr class="separator:gaf6a4e05c5b6141f00bdfa2ae1f30b15a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabe478d42590c0365f3e2feb3933321ec"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gabe478d42590c0365f3e2feb3933321ec">XHdmiphy1_WaitUs</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u32 MicroSeconds)</td></tr>
<tr class="memdesc:gabe478d42590c0365f3e2feb3933321ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the delay/sleep function for the <a class="el" href="struct_x_hdmiphy1.html" title="The XHdmiphy1 driver instance data. ">XHdmiphy1</a> driver.  <a href="group__xhdmiphy1.html#gabe478d42590c0365f3e2feb3933321ec">More...</a><br/></td></tr>
<tr class="separator:gabe478d42590c0365f3e2feb3933321ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga71a574c5aedf401c9b7c59a173822f8f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga71a574c5aedf401c9b7c59a173822f8f">XHdmiphy1_CfgLineRate</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u64 LineRateHz)</td></tr>
<tr class="memdesc:ga71a574c5aedf401c9b7c59a173822f8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the channel's line rate.  <a href="group__xhdmiphy1.html#ga71a574c5aedf401c9b7c59a173822f8f">More...</a><br/></td></tr>
<tr class="separator:ga71a574c5aedf401c9b7c59a173822f8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97e1d4070dafe5a73d9bf60621382c98"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gae8559ee2ca7c404467a72f4653a5d4f5">XHdmiphy1_PllType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga97e1d4070dafe5a73d9bf60621382c98">XHdmiphy1_GetPllType</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:ga97e1d4070dafe5a73d9bf60621382c98"><td class="mdescLeft">&#160;</td><td class="mdescRight">Obtain the channel's PLL reference clock selection.  <a href="group__xhdmiphy1.html#ga97e1d4070dafe5a73d9bf60621382c98">More...</a><br/></td></tr>
<tr class="separator:ga97e1d4070dafe5a73d9bf60621382c98"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga31263f99c22623f852ea864fba080232"><td class="memItemLeft" align="right" valign="top">u64&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga31263f99c22623f852ea864fba080232">XHdmiphy1_GetLineRateHz</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:ga31263f99c22623f852ea864fba080232"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will return the line rate in Hz for a given channel / quad.  <a href="group__xhdmiphy1.html#ga31263f99c22623f852ea864fba080232">More...</a><br/></td></tr>
<tr class="separator:ga31263f99c22623f852ea864fba080232"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7f1f22be7f2029c396c015e322475790"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga7f1f22be7f2029c396c015e322475790">XHdmiphy1_ResetGtPll</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, u8 Hold)</td></tr>
<tr class="memdesc:ga7f1f22be7f2029c396c015e322475790"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will reset the GT's PLL logic.  <a href="group__xhdmiphy1.html#ga7f1f22be7f2029c396c015e322475790">More...</a><br/></td></tr>
<tr class="separator:ga7f1f22be7f2029c396c015e322475790"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga117b1b06a6044a0574731e960e8e304a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga117b1b06a6044a0574731e960e8e304a">XHdmiphy1_ResetGtTxRx</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, u8 Hold)</td></tr>
<tr class="memdesc:ga117b1b06a6044a0574731e960e8e304a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will reset the GT's TX/RX logic.  <a href="group__xhdmiphy1.html#ga117b1b06a6044a0574731e960e8e304a">More...</a><br/></td></tr>
<tr class="separator:ga117b1b06a6044a0574731e960e8e304a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga615fe597062a12b286153f2ee8007e91"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga615fe597062a12b286153f2ee8007e91">XHdmiphy1_SetPolarity</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, u8 Polarity)</td></tr>
<tr class="memdesc:ga615fe597062a12b286153f2ee8007e91"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set/clear the TX/RX polarity bit.  <a href="group__xhdmiphy1.html#ga615fe597062a12b286153f2ee8007e91">More...</a><br/></td></tr>
<tr class="separator:ga615fe597062a12b286153f2ee8007e91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga041ec28c400f1b4cb662d9670e0feff3"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga041ec28c400f1b4cb662d9670e0feff3">XHdmiphy1_SetPrbsSel</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, <a class="el" href="group__xhdmiphy1.html#ga3532b332baefc7e9454c8d485aedb4c9">XHdmiphy1_PrbsPattern</a> Pattern)</td></tr>
<tr class="memdesc:ga041ec28c400f1b4cb662d9670e0feff3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the TX/RXPRBSEL of the GT.  <a href="group__xhdmiphy1.html#ga041ec28c400f1b4cb662d9670e0feff3">More...</a><br/></td></tr>
<tr class="separator:ga041ec28c400f1b4cb662d9670e0feff3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae474ac8f1f2997229ec25e7584a4b827"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gae474ac8f1f2997229ec25e7584a4b827">XHdmiphy1_TxPrbsForceError</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 ForceErr)</td></tr>
<tr class="memdesc:gae474ac8f1f2997229ec25e7584a4b827"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the TX/RXPRBSEL of the GT.  <a href="group__xhdmiphy1.html#gae474ac8f1f2997229ec25e7584a4b827">More...</a><br/></td></tr>
<tr class="separator:gae474ac8f1f2997229ec25e7584a4b827"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa01b2c0214336ba205fcac3c8fd7675d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaa01b2c0214336ba205fcac3c8fd7675d">XHdmiphy1_SetTxVoltageSwing</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Vs)</td></tr>
<tr class="memdesc:gaa01b2c0214336ba205fcac3c8fd7675d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the TX voltage swing value for a given channel.  <a href="group__xhdmiphy1.html#gaa01b2c0214336ba205fcac3c8fd7675d">More...</a><br/></td></tr>
<tr class="separator:gaa01b2c0214336ba205fcac3c8fd7675d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9dd0d271c9be7416e55adc535257cea"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gad9dd0d271c9be7416e55adc535257cea">XHdmiphy1_SetTxPreEmphasis</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Pe)</td></tr>
<tr class="memdesc:gad9dd0d271c9be7416e55adc535257cea"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the TX pre-emphasis value for a given channel.  <a href="group__xhdmiphy1.html#gad9dd0d271c9be7416e55adc535257cea">More...</a><br/></td></tr>
<tr class="separator:gad9dd0d271c9be7416e55adc535257cea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga755a209f0abe848a3508017f83ad4c62"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga755a209f0abe848a3508017f83ad4c62">XHdmiphy1_SetTxPostCursor</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u8 Pc)</td></tr>
<tr class="memdesc:ga755a209f0abe848a3508017f83ad4c62"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will set the TX post-curosr value for a given channel.  <a href="group__xhdmiphy1.html#ga755a209f0abe848a3508017f83ad4c62">More...</a><br/></td></tr>
<tr class="separator:ga755a209f0abe848a3508017f83ad4c62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga704b9c7161c4ac92beaa07113caaa36c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga704b9c7161c4ac92beaa07113caaa36c">XHdmiphy1_SetRxLpm</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, u8 Enable)</td></tr>
<tr class="memdesc:ga704b9c7161c4ac92beaa07113caaa36c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will enable or disable the LPM logic in the Video PHY core.  <a href="group__xhdmiphy1.html#ga704b9c7161c4ac92beaa07113caaa36c">More...</a><br/></td></tr>
<tr class="separator:ga704b9c7161c4ac92beaa07113caaa36c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga632197e5f773491cdf96f076e7112e0f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga632197e5f773491cdf96f076e7112e0f">XHdmiphy1_DrpWr</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u16 Addr, u16 Val)</td></tr>
<tr class="memdesc:ga632197e5f773491cdf96f076e7112e0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will initiate a write DRP transaction.  <a href="group__xhdmiphy1.html#ga632197e5f773491cdf96f076e7112e0f">More...</a><br/></td></tr>
<tr class="separator:ga632197e5f773491cdf96f076e7112e0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga55c5c6061828e1f986b64d4c0ae9a57b"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga55c5c6061828e1f986b64d4c0ae9a57b">XHdmiphy1_DrpRd</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, u16 Addr, u16 *RetVal)</td></tr>
<tr class="memdesc:ga55c5c6061828e1f986b64d4c0ae9a57b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will initiate a read DRP transaction.  <a href="group__xhdmiphy1.html#ga55c5c6061828e1f986b64d4c0ae9a57b">More...</a><br/></td></tr>
<tr class="separator:ga55c5c6061828e1f986b64d4c0ae9a57b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga13859cf616b98f6d37336128b9f3f21a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga13859cf616b98f6d37336128b9f3f21a">XHdmiphy1_MmcmPowerDown</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Hold)</td></tr>
<tr class="memdesc:ga13859cf616b98f6d37336128b9f3f21a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will power down the mixed-mode clock manager (MMCM) core.  <a href="group__xhdmiphy1.html#ga13859cf616b98f6d37336128b9f3f21a">More...</a><br/></td></tr>
<tr class="separator:ga13859cf616b98f6d37336128b9f3f21a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5dc7ec503e2e78570719440c12773984"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga5dc7ec503e2e78570719440c12773984">XHdmiphy1_MmcmStart</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:ga5dc7ec503e2e78570719440c12773984"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will start the mixed-mode clock manager (MMCM) core.  <a href="group__xhdmiphy1.html#ga5dc7ec503e2e78570719440c12773984">More...</a><br/></td></tr>
<tr class="separator:ga5dc7ec503e2e78570719440c12773984"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga57aac6b723825d9999dc5419d067bda3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga57aac6b723825d9999dc5419d067bda3">XHdmiphy1_IBufDsEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Enable)</td></tr>
<tr class="memdesc:ga57aac6b723825d9999dc5419d067bda3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the TX or RX IBUFDS peripheral.  <a href="group__xhdmiphy1.html#ga57aac6b723825d9999dc5419d067bda3">More...</a><br/></td></tr>
<tr class="separator:ga57aac6b723825d9999dc5419d067bda3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab511031505e9679f2bd243d68eb725f4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gab511031505e9679f2bd243d68eb725f4">XHdmiphy1_Clkout1OBufTdsEnable</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, XHdmiphy1_DirectionType Dir, u8 Enable)</td></tr>
<tr class="memdesc:gab511031505e9679f2bd243d68eb725f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the TX or RX CLKOUT1 OBUFTDS peripheral.  <a href="group__xhdmiphy1.html#gab511031505e9679f2bd243d68eb725f4">More...</a><br/></td></tr>
<tr class="separator:gab511031505e9679f2bd243d68eb725f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90147f575dee01a888964ba10cdf4f73"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga90147f575dee01a888964ba10cdf4f73">XHdmiphy1_SetErrorCallback</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, void *CallbackFunc, void *CallbackRef)</td></tr>
<tr class="memdesc:ga90147f575dee01a888964ba10cdf4f73"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function installs a callback function for the HDMIPHY error conditions.  <a href="group__xhdmiphy1.html#ga90147f575dee01a888964ba10cdf4f73">More...</a><br/></td></tr>
<tr class="separator:ga90147f575dee01a888964ba10cdf4f73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7efb70724bc3a6fa0d3bd6c9d7d22de4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga7efb70724bc3a6fa0d3bd6c9d7d22de4">XHdmiphy1_SetLogCallback</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u64 *CallbackFunc, void *CallbackRef)</td></tr>
<tr class="memdesc:ga7efb70724bc3a6fa0d3bd6c9d7d22de4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function installs an asynchronous callback function for the LogWrite API:  <a href="group__xhdmiphy1.html#ga7efb70724bc3a6fa0d3bd6c9d7d22de4">More...</a><br/></td></tr>
<tr class="separator:ga7efb70724bc3a6fa0d3bd6c9d7d22de4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9569d5080ff8e2396239ecfb7d1de91d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga9569d5080ff8e2396239ecfb7d1de91d">XHdmiphy1_LogDisplay</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga9569d5080ff8e2396239ecfb7d1de91d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will print the entire log.  <a href="group__xhdmiphy1.html#ga9569d5080ff8e2396239ecfb7d1de91d">More...</a><br/></td></tr>
<tr class="separator:ga9569d5080ff8e2396239ecfb7d1de91d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga67dcfc543f278ca875c99f6dada92520"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga67dcfc543f278ca875c99f6dada92520">XHdmiphy1_LogReset</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga67dcfc543f278ca875c99f6dada92520"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will reset the driver's logginc mechanism.  <a href="group__xhdmiphy1.html#ga67dcfc543f278ca875c99f6dada92520">More...</a><br/></td></tr>
<tr class="separator:ga67dcfc543f278ca875c99f6dada92520"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafef83d134d6ba3cf7ed6ff58c5aa76c0"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gafef83d134d6ba3cf7ed6ff58c5aa76c0">XHdmiphy1_LogRead</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:gafef83d134d6ba3cf7ed6ff58c5aa76c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will read the last event from the log.  <a href="group__xhdmiphy1.html#gafef83d134d6ba3cf7ed6ff58c5aa76c0">More...</a><br/></td></tr>
<tr class="separator:gafef83d134d6ba3cf7ed6ff58c5aa76c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabda0c5df35f1e8c13b871c8edf38ff38"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gabda0c5df35f1e8c13b871c8edf38ff38">XHdmiphy1_LogWrite</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga507763f75897762cabf8819fde24ab8f">XHdmiphy1_LogEvent</a> Evt, u8 Data)</td></tr>
<tr class="memdesc:gabda0c5df35f1e8c13b871c8edf38ff38"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will insert an event in the driver's logginc mechanism.  <a href="group__xhdmiphy1.html#gabda0c5df35f1e8c13b871c8edf38ff38">More...</a><br/></td></tr>
<tr class="separator:gabda0c5df35f1e8c13b871c8edf38ff38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb93fcb29ad3045d260d3fbbaa0be81e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gacb93fcb29ad3045d260d3fbbaa0be81e">XHdmiphy1_InterruptHandler</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:gacb93fcb29ad3045d260d3fbbaa0be81e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the interrupt handler for the <a class="el" href="struct_x_hdmiphy1.html" title="The XHdmiphy1 driver instance data. ">XHdmiphy1</a> driver.  <a href="group__xhdmiphy1.html#gacb93fcb29ad3045d260d3fbbaa0be81e">More...</a><br/></td></tr>
<tr class="separator:gacb93fcb29ad3045d260d3fbbaa0be81e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga08947cfedb541b7f95242c82ee60a8c5"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga08947cfedb541b7f95242c82ee60a8c5">XHdmiphy1_SelfTest</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga08947cfedb541b7f95242c82ee60a8c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function runs a self-test on the <a class="el" href="struct_x_hdmiphy1.html" title="The XHdmiphy1 driver instance data. ">XHdmiphy1</a> driver/device.  <a href="group__xhdmiphy1.html#ga08947cfedb541b7f95242c82ee60a8c5">More...</a><br/></td></tr>
<tr class="separator:ga08947cfedb541b7f95242c82ee60a8c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00ae2fd009178f0fbdefc1764abdea0f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_hdmiphy1___config.html">XHdmiphy1_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga00ae2fd009178f0fbdefc1764abdea0f">XHdmiphy1_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:ga00ae2fd009178f0fbdefc1764abdea0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function looks for the device configuration based on the unique device ID.  <a href="group__xhdmiphy1.html#ga00ae2fd009178f0fbdefc1764abdea0f">More...</a><br/></td></tr>
<tr class="separator:ga00ae2fd009178f0fbdefc1764abdea0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa15dd35a9b1670aab091738d3ecca9df"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">XHdmiphy1_Hdmi_CfgInitialize</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="struct_x_hdmiphy1___config.html">XHdmiphy1_Config</a> *CfgPtr)</td></tr>
<tr class="memdesc:gaa15dd35a9b1670aab091738d3ecca9df"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initializes the Video PHY for HDMI.  <a href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">More...</a><br/></td></tr>
<tr class="separator:gaa15dd35a9b1670aab091738d3ecca9df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga69e679f0c4444350910817be69cde77c"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga69e679f0c4444350910817be69cde77c">XHdmiphy1_SetHdmiTxParam</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XVidC_PixelsPerClock Ppc, XVidC_ColorDepth Bpc, XVidC_ColorFormat ColorFormat)</td></tr>
<tr class="memdesc:ga69e679f0c4444350910817be69cde77c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function update/set the HDMI TX parameter.  <a href="group__xhdmiphy1.html#ga69e679f0c4444350910817be69cde77c">More...</a><br/></td></tr>
<tr class="separator:ga69e679f0c4444350910817be69cde77c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2bf27809a22eecc5194a8bad16261280"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga2bf27809a22eecc5194a8bad16261280">XHdmiphy1_SetHdmiRxParam</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:ga2bf27809a22eecc5194a8bad16261280"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function update/set the HDMI RX parameter.  <a href="group__xhdmiphy1.html#ga2bf27809a22eecc5194a8bad16261280">More...</a><br/></td></tr>
<tr class="separator:ga2bf27809a22eecc5194a8bad16261280"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa361514e8315c25876867a1ded2c99b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gafa361514e8315c25876867a1ded2c99b">XHdmiphy1_HdmiCfgCalcMmcmParam</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId, XHdmiphy1_DirectionType Dir, XVidC_PixelsPerClock Ppc, XVidC_ColorDepth Bpc)</td></tr>
<tr class="memdesc:gafa361514e8315c25876867a1ded2c99b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function calculates the HDMI MMCM parameters.  <a href="group__xhdmiphy1.html#gafa361514e8315c25876867a1ded2c99b">More...</a><br/></td></tr>
<tr class="separator:gafa361514e8315c25876867a1ded2c99b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d8702f582054727e5bafc4e6cf32739"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga1d8702f582054727e5bafc4e6cf32739">XHdmiphy1_HdmiUpdateClockSelection</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a> TxSysPllClkSel, <a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a> RxSysPllClkSel)</td></tr>
<tr class="memdesc:ga1d8702f582054727e5bafc4e6cf32739"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function Updates the HDMIPHY clocking.  <a href="group__xhdmiphy1.html#ga1d8702f582054727e5bafc4e6cf32739">More...</a><br/></td></tr>
<tr class="separator:ga1d8702f582054727e5bafc4e6cf32739"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac39e0926826a1e127514c8350ddcde21"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gac39e0926826a1e127514c8350ddcde21">XHdmiphy1_ClkDetFreqReset</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:gac39e0926826a1e127514c8350ddcde21"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets clock detector TX/RX frequency.  <a href="group__xhdmiphy1.html#gac39e0926826a1e127514c8350ddcde21">More...</a><br/></td></tr>
<tr class="separator:gac39e0926826a1e127514c8350ddcde21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb75647ab6dfd99febccba18593e86d8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gabb75647ab6dfd99febccba18593e86d8">XHdmiphy1_ClkDetGetRefClkFreqHz</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:gabb75647ab6dfd99febccba18593e86d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the frequency of the RX/TX reference clock as measured by the clock detector peripheral.  <a href="group__xhdmiphy1.html#gabb75647ab6dfd99febccba18593e86d8">More...</a><br/></td></tr>
<tr class="separator:gabb75647ab6dfd99febccba18593e86d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae2d190888890d12b1524b5d5065e5e57"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#gae2d190888890d12b1524b5d5065e5e57">XHdmiphy1_DruGetRefClkFreqHz</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:gae2d190888890d12b1524b5d5065e5e57"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the frequency of the DRU reference clock as measured by the clock detector peripheral.  <a href="group__xhdmiphy1.html#gae2d190888890d12b1524b5d5065e5e57">More...</a><br/></td></tr>
<tr class="separator:gae2d190888890d12b1524b5d5065e5e57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16dfea31e43d9da2c4c00cd0785b6248"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">XHdmiphy1_HdmiDebugInfo</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, <a class="el" href="group__xhdmiphy1.html#ga54f72201d2012e3c638ec92b5e310f23">XHdmiphy1_ChannelId</a> ChId)</td></tr>
<tr class="memdesc:ga16dfea31e43d9da2c4c00cd0785b6248"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints Video PHY debug information related to HDMI.  <a href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">More...</a><br/></td></tr>
<tr class="separator:ga16dfea31e43d9da2c4c00cd0785b6248"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64e64512cb8f987620763078fe9e796d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga64e64512cb8f987620763078fe9e796d">XHdmiphy1_SetHdmiCallback</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, <a class="el" href="group__xhdmiphy1.html#ga8df8a80a15683dd3ffe31d80780f6329">XHdmiphy1_HdmiHandlerType</a> HandlerType, void *CallbackFunc, void *CallbackRef)</td></tr>
<tr class="memdesc:ga64e64512cb8f987620763078fe9e796d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function installs an HDMI callback function for the specified handler type.  <a href="group__xhdmiphy1.html#ga64e64512cb8f987620763078fe9e796d">More...</a><br/></td></tr>
<tr class="separator:ga64e64512cb8f987620763078fe9e796d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e17b8f3099b9edb96bdf732671b7efc"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga1e17b8f3099b9edb96bdf732671b7efc">XHdmiphy1_Hdmi20Config</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)</td></tr>
<tr class="memdesc:ga1e17b8f3099b9edb96bdf732671b7efc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will configure the HDMIPHY to HDMI 2.0 mode.  <a href="group__xhdmiphy1.html#ga1e17b8f3099b9edb96bdf732671b7efc">More...</a><br/></td></tr>
<tr class="separator:ga1e17b8f3099b9edb96bdf732671b7efc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2aa401218d0bc4c64c2210f85ccee457"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga2aa401218d0bc4c64c2210f85ccee457">XHdmiphy1_Hdmi21Config</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u64 LineRate, u8 NChannels)</td></tr>
<tr class="memdesc:ga2aa401218d0bc4c64c2210f85ccee457"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function will configure the GT for HDMI 2.1 operation.  <a href="group__xhdmiphy1.html#ga2aa401218d0bc4c64c2210f85ccee457">More...</a><br/></td></tr>
<tr class="separator:ga2aa401218d0bc4c64c2210f85ccee457"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8dc19df05e15d413e62ff62d2c22c023"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xhdmiphy1.html#ga8dc19df05e15d413e62ff62d2c22c023">XHdmiphy1_RegisterDebug</a> (<a class="el" href="struct_x_hdmiphy1.html">XHdmiphy1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga8dc19df05e15d413e62ff62d2c22c023"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints out Video PHY register and GT Channel and Common DRP register contents.  <a href="group__xhdmiphy1.html#ga8dc19df05e15d413e62ff62d2c22c023">More...</a><br/></td></tr>
<tr class="separator:ga8dc19df05e15d413e62ff62d2c22c023"><td class="memSeparator" colspan="2">&#160;</td></tr>
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